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/* This file has been prepared for Doxygen automatic documentation generation.*/
/******************************************************************************/
//! \name Output pins to drive stages.
#define UL PB0
#define VL PB6
#define WL PB7
#define UH PD5
#define VH PD6
#define WH PD7
#define MC_MASK ((0<<UL)|(0<<VL)|(0<<WL)|(1<<UH)|(1<<VH)|(1<<WH))
//! \name Hall sensor input pins.
//@{
#define HALL1 0 // PB3
#define HALL2 1 //PB4
#define HALL3 2 //PB5
#define HALL_MASK ((1<<HALL1)|(1<<HALL2)|(1<<HALL3))
#define HP1 ((0<<HALL1)|(1<<HALL2)|(0<<HALL3)) //5
#define HP2 ((0<<HALL1)|(1<<HALL2)|(1<<HALL3)) //4
#define HP3 ((0<<HALL1)|(0<<HALL2)|(1<<HALL3)) //6
#define HP4 ((1<<HALL1)|(0<<HALL2)|(1<<HALL3)) //2
#define HP5 ((1<<HALL1)|(0<<HALL2)|(0<<HALL3)) //3
#define HP6 ((1<<HALL1)|(1<<HALL2)|(0<<HALL3)) //1
//20070728
#define PDP1_CW ((1<<UH)|(1<<VH)|(0<<WH))
#define PDP2_CW ((1<<UH)|(0<<VH)|(1<<WH))
#define PDP3_CW ((1<<UH)|(0<<VH)|(1<<WH))
#define PDP4_CW ((0<<UH)|(1<<VH)|(1<<WH))
#define PDP5_CW ((1<<UH)|(1<<VH)|(0<<WH))
#define PDP6_CW ((0<<UH)|(1<<VH)|(1<<WH))
#define PDP_stop ((1<<UH)|(1<<VH)|(1<<WH))
#define PBP1_CW ((0<<UL)|(1<<VL)|(1<<WL))
#define PBP2_CW ((1<<UL)|(1<<VL)|(0<<WL))
#define PBP3_CW ((0<<UL)|(1<<VL)|(1<<WL))
#define PBP4_CW ((1<<UL)|(0<<VL)|(1<<WL))
#define PBP5_CW ((1<<UL)|(0<<VL)|(1<<WL))
#define PBP6_CW ((1<<UL)|(1<<VL)|(0<<WL))
#define PBP_stop ((1<<UL)|(1<<VL)|(1<<WL))
#define PDP1_ANCW ((0<<UH)|(1<<VH)|(1<<WH))
#define PDP2_ANCW ((1<<UH)|(0<<VH)|(1<<WH))
#define PDP3_ANCW ((1<<UH)|(0<<VH)|(1<<WH))
#define PDP4_ANCW ((1<<UH)|(1<<VH)|(0<<WH))
#define PDP5_ANCW ((0<<UH)|(1<<VH)|(1<<WH))
#define PDP6_ANCW ((1<<UH)|(1<<VH)|(0<<WH))
#define PBP1_ANCW ((1<<UL)|(1<<VL)|(0<<WL))
#define PBP2_ANCW ((0<<UL)|(1<<VL)|(1<<WL))
#define PBP3_ANCW ((1<<UL)|(1<<VL)|(0<<WL))
#define PBP4_ANCW ((1<<UL)|(0<<VL)|(1<<WL))
#define PBP5_ANCW ((1<<UL)|(0<<VL)|(1<<WL))
#define PBP6_ANCW ((0<<UL)|(1<<VL)|(1<<WL))
const unsigned char HAll_CW[] = {
0,
3, // ((1<<HALL1)|(0<<HALL2)|(1<<HALL3))
6, // ((1<<HALL1)|(0<<HALL2)|(0<<HALL3))
2, // ((1<<HALL1)|(1<<HALL2)|(0<<HALL3))
5, // ((0<<HALL1)|(1<<HALL2)|(0<<HALL3))
1, // ((0<<HALL1)|(1<<HALL2)|(1<<HALL3))
4, // ((0<<HALL1)|(0<<HALL2)|(1<<HALL3))
7,
};
//b
const unsigned char PDP_CW[] = {
// MC_PORT drive config
PDP_stop,
PDP5_CW, // ((0<<UH)|(1<<VH)|(0<<WH))
PDP6_CW, // ((1<<UH)|(0<<VH)|(0<<WH))
PDP4_CW, // ((1<<UH)|(0<<VH)|(0<<WH))
PDP3_CW, // ((0<<UH)|(0<<VH)|(1<<WH))
PDP1_CW, // ((0<<UH)|(1<<VH)|(0<<WH))
PDP2_CW, // ((0<<UH)|(0<<VH)|(1<<WH))
PDP_stop , // ((1<<UH)|(1<<VH)|(1<<WH))
};
const unsigned char PBP_CW[] = {
// MC_PORT drive config
PBP_stop,
PBP5_CW, // ((1<<UL)|(1<<VL)|(0<<WL))
PBP6_CW, // ((1<<UL)|(0<<VL)|(1<<WL))
PBP4_CW, // ((1<<UL)|(1<<VL)|(0<<WL))
PBP3_CW, // ((0<<UL)|(1<<VL)|(1<<WL))
PBP1_CW, // ((0<<UL)|(1<<VL)|(1<<WL))
PBP2_CW, // ((1<<UL)|(0<<VL)|(1<<WL))
PBP_stop, // ((0<<UL)|(0<<VL)|(0<<WL))
};
//-----------------------------------------------------------------
const unsigned char HAll_ANCW[] = {
0,
5, // ((0<<HALL1)|(0<<HALL2)|(1<<HALL3))
3, // ((1<<HALL1)|(0<<HALL2)|(1<<HALL3))
1, // ((1<<HALL1)|(0<<HALL2)|(0<<HALL3))
6, // ((1<<HALL1)|(1<<HALL2)|(0<<HALL3))
4, // ((0<<HALL1)|(1<<HALL2)|(0<<HALL3))
2, // ((0<<HALL1)|(1<<HALL2)|(1<<HALL3))
7,
};
//b
const unsigned char PDP_ANCW[] = {
// MC_PORT drive config
PDP_stop,
PDP3_ANCW,
PDP6_ANCW,
PDP2_ANCW,
PDP5_ANCW,
PDP1_ANCW,
PDP4_ANCW,
PDP_stop ,
};
const unsigned char PBP_ANCW[] = {
// MC_PORT drive config
PBP_stop,
PBP3_ANCW,
PBP6_ANCW,
PBP2_ANCW,
PBP5_ANCW,
PBP1_ANCW,
PBP4_ANCW,
PBP_stop, // ((0<<UL)|(0<<VL)|(0<<WL))
}; |
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