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发表于 2016-8-3 14:48
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本帖最后由 zcm550667797 于 2016-8-3 14:54 编辑
MaxwellProject (E:/workbench project/ycdj2_files/dpall/global/Ansoft/)
Maxwell3DDesign1 (Transient)
[error] Assignment of 'RA_1' and assignment of 'RB_1' contain same entity. (2:44:20 下午 八月 03, 2016)
[error] Assignment of 'RA_2' and assignment of 'RB_2' contain same entity. (2:44:20 下午 八月 03, 2016)
[error] Assignment of 'RA_3' and assignment of 'RB_3' contain same entity. (2:44:20 下午 八月 03, 2016)
[error] Assignment of 'RA_4' and assignment of 'RB_4' contain same entity. (2:44:20 下午 八月 03, 2016)
[error] Assignment of 'RA_5' and assignment of 'RB_5' contain same entity. (2:44:20 下午 八月 03, 2016)
[error] Assignment of 'RA_6' and assignment of 'RB_6' contain same entity. (2:44:20 下午 八月 03, 2016)
[error] Illegal Overlap: some boundaries or excitations are assigned on the same entity. To continue, please resolve this condition. (2:44:20 下午 八月 03, 2016)
[error] Simulation completed with execution error on server: Local Machine. (2:44:20 下午 八月 03, 2016)
[info] DesignXplorer Analysis on DefaultDesignXplorerSetup has been started. (2:44:20 下午 八月 03, 2016)
[info] A variation (nominal) has been requested on machine Local Machine (2:44:21 下午 八月 03, 2016)
[error] Assignment of 'RA_1' and assignment of 'RB_1' contain same entity. (2:44:22 下午 八月 03, 2016)
[error] Assignment of 'RA_2' and assignment of 'RB_2' contain same entity. (2:44:22 下午 八月 03, 2016)
[error] Assignment of 'RA_3' and assignment of 'RB_3' contain same entity. (2:44:22 下午 八月 03, 2016)
[error] Assignment of 'RA_4' and assignment of 'RB_4' contain same entity. (2:44:22 下午 八月 03, 2016)
[error] Assignment of 'RA_5' and assignment of 'RB_5' contain same entity. (2:44:22 下午 八月 03, 2016)
[error] Assignment of 'RA_6' and assignment of 'RB_6' contain same entity. (2:44:22 下午 八月 03, 2016)
[error] Illegal Overlap: some boundaries or excitations are assigned on the same entity. To continue, please resolve this condition. (2:44:22 下午 八月 03, 2016)
[info] DesignXplorer Analysis is done. (2:44:22 下午 八月 03, 2016)
[error] Error encountered in generating DesignXplorer analysis result file. (2:44:22 下午 八月 03, 2016)
问题:
1.我不知道以上的error怎么解决,我看模型的RA\RB绕组没有重合,没有contain same entity,好奇怪
2.我不知道全模型的边界怎么加好一点,我看了很多1/2和1/4模型可以加master boundary 和slave boundary,全模型只能zero tangential H Field边界
3.vaildation check时候,提示边界有问题,我设置了zero tangential H Field边界,还是一样
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帮我看看
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