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- 1970-1-1
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楼主 |
发表于 2015-4-13 12:53
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TIM配置代码如下:
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
TIM_OCInitTypeDef TIM_OCInitStructure;
TIM_BDTRInitTypeDef TIM_BDTRInitStructure;
//#if DRIVE_AUTO_OUTPUT_LOW_SIDE <= 0
// TIM_BDTRInitTypeDef TIM_BDTRInitStructure;
//#endif
TIM1_RCC_Configuration();
TIM1_GPIO_Configuration();
/* Time Base configuration */
TIM_DeInit(TIMER_NUM);
TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.TIM_Prescaler = PWM_PRSC;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_CenterAligned1;
TIM_TimeBaseStructure.TIM_Period = PWM_PERIOD-1;
TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV2;
TIM_TimeBaseStructure.TIM_RepetitionCounter = REP_RATE;
TIM_TimeBaseInit(TIMER_NUM, &TIM_TimeBaseStructure);
/* Channel 1 Configuration in PWM mode */
TIM_OCStructInit(&TIM_OCInitStructure);
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
#if PMOS_ON_HIGH_SIDE > 0
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_Low;
TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
#else
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Reset;
#endif
#if DRIVE_AUTO_OUTPUT_LOW_SIDE <= 0
TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Enable;
TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High;
TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCNIdleState_Reset;
#else
TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Disable;
TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_High;
TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCNIdleState_Reset;
#endif
TIM_OCInitStructure.TIM_Pulse = 0;
TIM_OC1Init(TIMER_NUM, &TIM_OCInitStructure);
TIM_OCInitStructure.TIM_Pulse = 0;
TIM_OC2Init(TIMER_NUM, &TIM_OCInitStructure);
TIM_OCInitStructure.TIM_Pulse = 0;
TIM_OC3Init(TIMER_NUM, &TIM_OCInitStructure);
/* Channel 4 Configuration in OC */
TIM_OCStructInit(&TIM_OCInitStructure);
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM2; //oí1.2.3í¨μàμÄPWM1Ä£ê½ÕyoÃÏà·′£¬2ο¼
// TIM1_CCMR1¼Ä′æÆ÷μÄ4-6λ¡£
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable; ////CCR4 Õa¸ö±ØDëêä3öê1Äüoó2ÅÄü′¥·¢ADC1μÄ×¢èëí¨μà2éÑù
TIM_OCInitStructure.TIM_OutputNState = TIM_OutputNState_Disable; // TIM_OutputState_Enable
TIM_OCInitStructure.TIM_Pulse = PWM_PERIOD -1;//2*PWM_PERIOD -20 - 30; //20Îaμçá÷2éÑùê±¼ä 30Îa±£Ö¤2éÑù걿ìÔútim ¸üDÂê¼t2úéú֮ǰ
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
TIM_OCInitStructure.TIM_OCNPolarity = TIM_OCNPolarity_Low;
TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Set;
TIM_OCInitStructure.TIM_OCNIdleState = TIM_OCIdleState_Reset;
TIM_OC4Init(TIMER_NUM, &TIM_OCInitStructure);
/* Enables the TIM1 Preload on CC1 Register */
TIM_OC1PreloadConfig(TIMER_NUM, TIM_OCPreload_Enable); //Æôóñè½ÏÆ÷μÄó°×ó¼Ä′æÆ÷£¨Ö±μ½2úéú¸üDÂê¼t2Ÿü¸ÄéèÖã©
/* Enables the TIM1 Preload on CC2 Register */
TIM_OC2PreloadConfig(TIMER_NUM, TIM_OCPreload_Enable);
/* Enables the TIM1 Preload on CC3 Register */
TIM_OC3PreloadConfig(TIMER_NUM, TIM_OCPreload_Enable);
/* Enables the TIM1 Preload on CC4 Register */
TIM_OC4PreloadConfig(TIMER_NUM, TIM_OCPreload_Enable);
//#if DRIVE_AUTO_OUTPUT_LOW_SIDE <= 0
/* Automatic Output enable, Break, dead time and lock configuration*/
TIM_BDTRInitStructure.TIM_OSSRState = TIM_OSSRState_Enable; //TIM_OSSRState_Enable TIM_OSSIState_Disable
TIM_BDTRInitStructure.TIM_OSSIState = TIM_OSSRState_Enable;
TIM_BDTRInitStructure.TIM_LOCKLevel = TIM_LOCKLevel_1;
TIM_BDTRInitStructure.TIM_DeadTime = TIMER_DeadTime_Value;//64;
TIM_BDTRInitStructure.TIM_Break = TIM_Break_Disable;
TIM_BDTRInitStructure.TIM_BreakPolarity = TIM_BreakPolarity_High;
TIM_BDTRInitStructure.TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
TIM_BDTRConfig(TIMER_NUM, &TIM_BDTRInitStructure);
//#endif
TIM_SelectOutputTrigger(TIMER_NUM, TIM_TRGOSource_Update); //Ñ¡ÔñTIM1′¥·¢Æ÷êä3öÄ£ê½
// TIM_SelectOutputTrigger(TIMER_NUM, TIM_TRGOSource_OC4Ref); //Ñ¡ÔñTIM1′¥·¢Æ÷êä3öÄ£ê½
// TIM_ClearITPendingBit(TIMER_NUM, TIM_IT_Break);//Çå3t½ô¼±é23μÖD¶Ï±ê־λ
// TIM_ITConfig(TIMER_NUM, TIM_IT_Break,DISABLE); //ENABLE ê1Äü½ô¼±é23μÖD¶Ï Ç°ÃæDèòaTIM1_BDTRInitStructure.TIM_Break = TIM_Break_Enable;
// // Clear Update Flag
// TIM_ClearFlag(TIMER_NUM, TIM_FLAG_Update);
////
// TIM_ITConfig(TIMER_NUM, TIM_IT_Update, ENABLE); //ÔúêÇ·ñDèòa¶áè¡ADCÖD¾ö¶¨1رջò¿aÆô¸üDÂê¼tÖD¶Ï
////
// TIM_ITConfig(TIMER_NUM, TIM_IT_CC4,ENABLE);
Motor_DRIVE_ON();
/* TIMER_NUM counter enable */
TIM_Cmd(TIMER_NUM, ENABLE);
/* Main Output Enable */
TIM_CtrlPWMOutputs(TIMER_NUM, ENABLE);
// Resynch to have the Update evend during Undeflow
TIM_GenerateEvent(TIMER_NUM, TIM_EventSource_Update); |
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