【VHDL-AMS】程序问题~~~

blackgarfield

下面是关于低噪声放大器(LNA)的一个vhdl-ams程序
但是只有ARCHITECTURE部分，缺少ENTITY部分，哪位大侠能给补全一下？
谢谢。。。

ARCHITECTURE stru_beha OF lna IS
       
        constant num:real_vector:=(0.0,3769911040.000000);
        constant den:real_vector:=(142517087507302055936.000000000,
                                                                3769911040.000000000,1.000000000);
        constant CAP:real:=701.67e-15;
        constant IND:real:=10.0e-9;
        constant R1:real:=9.75;
        constant R2:real:=40.25;
        constant GAIN_OF_G:real:=22.1E-3;
        constant GAIN:real:=7.146;
        constant ALPHA_1:real:=1.0;
        constant ALPHA_2:real:=1.0;
        constant ALPHA_3:real:=0.1183;
        quantity vin across iin through input to electrical_ref;
        quantity vout across iout through output to electrical_ref;
        terminal t1, t2, t3, t4, t5: electrical;
        quantity v_lap_in across i_lap_in through t2 to electrical_ref;
        quantity v_lap_out across i_lap_out through t4 to electrical_ref;
        quantity v_after_5 across t5 to electrical_ref;

BEGIN
        L1: entity work.inductor(ideal)
                generic map(ind => IND)
                port map   (p1=> input,p2=> t1)
        C1: entity work.capacitor(ideal)
                generic map( cap => CAP)
                port map   (p1=> t1,p2=> t2)
        R1: entity work.resistor(noisy)
                generic map( res =>R1)
                port map   (p1 => t2, p2=> t3)
        R2         entity work.resistor(ideal)
                generic map(res =>R2)
                port map   ( p1 => t3, p2 => electrical_ref)
        v_lap_out=v_lap_in'ltf(num,den);
        v_out_5 = GAIN*v_lap_out;
        vout = v_out_5*ALPHA_1+v_out_5*v_out_5*ALPHA_2
                        +v_out_5*v_out_5*v_out_5*ALPHA_3

END ARCHITECTURE stru_beha;