spice零件庫匯入問題
各位大神小弟這裡有個關於simplorer匯入spice零件庫的問題想請教...
我有匯入TI 的DRV3201Q1但有些BUG，其中最後還有一個錯誤不清楚在那裡
不知那位大神有碰過這個狀況?
系統訊息:
SimModel, Line 45 : Exception in CreateModelStructure(11:45:39 上午八月 23, 2016)
程式:
* DRV3201Q1
*****************************************************************************
* (C) Copyright 2014 Texas Instruments Incorporated. All rights reserved.
*****************************************************************************
** This model is designed as an aid for customers of Texas Instruments.
** TI and its licensors and suppliers make no warranties, either expressed
** or implied, with respect to this model, including the warranties of
** merchantability or fitness for a particular purpose.The model is
** provided solely on an "as is" basis.The entire risk as to its quality
** and performance is with the customer.
*****************************************************************************
*
** Released by: WEBENCH(R) Design Center, Texas Instruments Inc.
* Part: DRV3201Q1
* Date: 01/10/2014
* Model Type: All In One
* Simulator: PSPIICE
* Simulator Version: 16.2.0.p001
* EVM Order Number: N/A
* EVM Users Guide:N/A
* Datasheet: SLVSBD6C ?MAY 2012 ?REVISED MAY 2013
*
* Model Version: 1.0
*
*****************************************************************************
*
* Updates:
*
* Version 1.0 : Release to Web
*
*****************************************************************************
* Notes:
* 1. The following parameters are modeled:
* Aol, GBP, Phase Margin, Slew Rate, Input Offset Voltage,
* Ouput Voltage Range, PSRR, CMRR
*
* 2. The following parameters are not modeled:
* Temperature variation
*
*****************************************************************************
.subckt DRV3201Q1 G1 G2 G3 G4 IN IP O1 O3 RO VDD VSS
XI0 G1 G2 G3 G4 IN IP O1 O3 RO VDD VSS DRV3201Q1_HT1<=======系統說這行有問題
.ends
.subckt ANALOG_BUFFER VOUT VIN
R0 VIN 0 1e9
R1 VOUT 0 1e9
E0 VOUT 0 VIN 0 1
.ends ANALOG_BUFFER
.subckt DRV3201Q1_AMP2_HT1 VCC VEE VINM VINP VOUT
XAHDLINV0 NET082 NET068 NET079 0 HPA_INV_IDEAL
XAHDLI29 NET082 NET68 NET074 sw_l4 PARAMS: VON=1.1
XAHDLI30 NET068 NET088 NET074 sw_l4 PARAMS: VON=1.1
XAHDLI25 VCC_INT NET0166 NET082 NET079 0 HPA_COMP_IDEAL
XI21 NET066 NET065 DRV3201Q1_CMRR_HT1
XI19 VCC_INT VEE_INT NET8 NET066 DRV3201Q1_PSRR_HT1
XI18 NET058 NET8 DRV3201Q1_Inoise_HT1
XI17 NET048 NET058 DRV3201Q1_Vnoise_HT1
XI10 VCC VEE VIMON DRV3201Q1_ILOAD_HT1
H2 VIMON 0 VCURSOURCEDETECT1
I5 VCC VEE 2.8e-3
I0 NET041 0 1e-15
I3 NET065 0 1e-15
R2 NET51 NET089 1
R9 VINP NET048 100e-3
R10 VINM NET8 100e-3
R1 VIMON 0 1e9
R3 NET0137 NET0113 1e3
R0 NET66 NET39 159.2e6
R4 NET15 NET45 1
R6 NET15 NET21 100e-3
C1 NET0137 0 25e-12
C7 0 NET048 10e-15
C8 NET8 0 10e-15
C6 NET048 NET8 10e-15
C0 NET39 NET66 1.333e-9
XI16 NET089 NET0137 ANALOG_BUFFER
XI13 VEE_INT VEE ANALOG_BUFFER
XI12 VCC_INT VCC ANALOG_BUFFER
XI23 NET0113 NET0171 ANALOG_BUFFER
XI11 NET0105 NET45 ANALOG_BUFFER
XI2 NET21 NET51 ANALOG_BUFFER
D7 NET0171 NET0116 DIDEAL1
D6 NET0135 NET0171 DIDEAL1
D2 NET46 NET041 DIDEAL1
D1 NET041 NET25 DIDEAL1
D4 NET065 NET27 DIDEAL1
D3 NET48 NET065 DIDEAL1
D5 NET70 NET51 DIDEAL1
D0 NET51 NET33 DIDEAL1
D9 NET15 NET44 DIDEAL1
D8 NET0105 NET40 DIDEAL1
V18 NET088 0 4
V16 NET0166 0 6
V17 NET079 0 5
V7 NET041 NET058 0
V12 VCC_INT NET0116 0
V14 NET0135 VEE_INT 0
V1 NET67 NET39
V9 NET40 NET15 800e-6
V2 NET66 0 0
V10 NET44 NET0105 2e-3
V3 NET46 VEE_INT -500e-3
V6 NET48 VEE_INT -500e-3
V0 NET39 NET0171
VE1 NET52 VEE_INT 500e-3
V5 VCC_INT NET27 -700e-3
V4 VCC_INT NET25 -700e-3
VCURSOURCEDETECT NET45 NET59 0
VCURSINKDETECT VOUT NET59 0
V19 NET68 0 4.5
GAHDLI6 NET66 NET67 VALUE { LIMIT(V(NET041,NET065)*63e-3, -10e-3, 10e-3) }
H0 NET074 NET33 POLY(1) Vcursourcedetect1e-91e-9001e-9000001e-9
H1 NET70 NET52 POLY(1) Vcursinkdetect1e-91e-9001e-9000001e-9
.ends DRV3201Q1_AMP2_HT1
.subckt DRV3201Q1_AMP1_HT1 VCC VEE VINM VINP VOUT
XAHDLINV0 NET082 NET068 NET079 0 HPA_INV_IDEAL
XAHDLI29 NET082 NET68 NET074 sw_l4 PARAMS: VON=1.1
XAHDLI30 NET068 NET088 NET074 sw_l4 PARAMS: VON=1.1
XAHDLI25 VCC_INT NET0166 NET082 NET079 0 HPA_COMP_IDEAL
XI21 NET066 NET065 DRV3201Q1_CMRR_HT1
XI19 VCC_INT VEE_INT NET8 NET066 DRV3201Q1_PSRR_HT1
XI18 NET058 NET8 DRV3201Q1_Inoise_HT1
XI17 NET048 NET058 DRV3201Q1_Vnoise_HT1
XI10 VCC VEE VIMON DRV3201Q1_ILOAD_HT1
H2 VIMON 0 VCURSOURCEDETECT1
I5 VCC VEE 2.3e-3
I0 NET041 0 1e-15
I3 NET065 0 1e-15
R3 NET0137 NET0113 1e3
R2 NET51 NET089 1
R1 VIMON 0 1e9
R4 NET15 NET45 1
R6 NET15 NET21 100e-3
R9 VINP NET048 100e-3
R10 VINM NET8 100e-3
R0 NET66 NET39 159.2e6
C1 NET0137 0 25e-12
C7 0 NET048 10e-15
C8 NET8 0 10e-15
C6 NET048 NET8 10e-15
C0 NET39 NET66 1.333e-9
XI23 NET0113 NET0171 ANALOG_BUFFER
XI16 NET089 NET0137 ANALOG_BUFFER
XI11 NET0105 NET45 ANALOG_BUFFER
XI2 NET21 NET51 ANALOG_BUFFER
XI13 VEE_INT VEE ANALOG_BUFFER
XI12 VCC_INT VCC ANALOG_BUFFER
D5 NET70 NET51 DIDEAL1
D0 NET51 NET33 DIDEAL1
D9 NET15 NET44 DIDEAL1
D8 NET0105 NET40 DIDEAL1
D7 NET0171 NET0116 DIDEAL1
D6 NET0135 NET0171 DIDEAL1
D2 NET46 NET041 DIDEAL1
D1 NET041 NET25 DIDEAL1
D4 NET065 NET27 DIDEAL1
D3 NET48 NET065 DIDEAL1
V18 NET088 0 4
V19 NET68 0 4.5
V16 NET0166 0 6
V17 NET079 0 5
V9 NET40 NET15 800e-6
V10 NET44 NET0105 6e-3
VE1 NET52 VEE_INT 500e-3
VCURSOURCEDETECT NET45 NET59 0
VCURSINKDETECT VOUT NET59 0
V7 NET041 NET058 0
V12 VCC_INT NET0116 0
V14 NET0135 VEE_INT 0
V1 NET67 NET39
V2 NET66 0 0
V3 NET46 VEE_INT -500e-3
V6 NET48 VEE_INT -500e-3
V0 NET39 NET0171
V5 VCC_INT NET27 1
V4 VCC_INT NET25 1
GAHDLI6 NET66 NET67 VALUE { LIMIT(V(NET041,NET065)*63e-3, -10e-3, 10e-3) }
H0 NET074 NET33 POLY(1) Vcursourcedetect1e-91e-9001e-9000001e-9
H1 NET70 NET52 POLY(1) Vcursinkdetect1e-91e-9001e-9000001e-9
.ends DRV3201Q1_AMP1_HT1
.subckt DRV3201Q1_HT1 G1 G2 G3 G4 IN IP O1 O3 RO VDD VSS
R4 RO NET12 1.25e3
R3 NET12 NET14 416.67
R2 NET14 NET16 833.33
R1 NET16 NET18 2.5e3
R0 NET18 O3 5e3
XAHDLI4 G4 NET23 NET12 sw_l4 PARAMS: VON=1.1
XAHDLI3 G3 NET23 NET14 sw_l4 PARAMS: VON=1.1
XAHDLI2 G2 NET23 NET16 sw_l4 PARAMS: VON=1.1
XAHDLI12 G1 NET23 NET18 sw_l4 PARAMS: VON=1.1
XI1 VDD VSS NET23 O1 O3 DRV3201Q1_AMP2_HT1
XI0 VDD VSS IN IP O1 DRV3201Q1_AMP1_HT1
.ends DRV3201Q1_HT1
.SUBCKT HPA_INV_IDEAL 1 2 VDD VSS
E1 2 0 VALUE = { IF( V(1)> (V(VDD)+V(VSS))/2, V(VSS), V(VDD) ) }
.ENDS
.SUBCKT HPA_COMP_IDEAL INP INN OUT VDD VSS
E1 OUT 0 VALUE = { IF( (V(INP) > V(INN)), V(VDD), V(VSS) ) }
.ENDS
.SUBCKT sw_l4 S A B PARAMS: VON=1.1
S1 A B S 0 VSWITCH2
.MODEL VSWITCH2 VSWITCH Roff=1e8 Ron=1 Voff=0.00 Von={VON}
.ENDS
.MODEL DIDEAL1 D N=0.1m
.SUBCKT DRV3201Q1_ILOAD_HT1VDD VSS VIMON
G1 VDD 0 VALUE = {IF(V(VIMON) >= 0,V(VIMON),0)}
G2 VSS 0 VALUE = {IF(V(VIMON) < 0,V(VIMON),0)}
.ENDS
.SUBCKT DRV3201Q1_Vnoise_HT1 A B
V1 A B 0
.ENDS
.SUBCKT DRV3201Q1_Inoise_HT1 A B
R1 A B 1G
.ENDS
.SUBCKT DRV3201Q1_PSRR_HT1 VDD VSS A B
X1 VDD VSS A B 0 PSRR_DUAL_NEW
+ PARAMS: PSRRP = 80 FPSRRP = 1k
+ PSRRN = 80 FPSRRN = 1k
.ENDS
.SUBCKT DRV3201Q1_CMRR_HT1 A B
X1 A B 0 CMRR_NEW PARAMS: CMRR = 80 FCMRR = 10K
.ENDS
.SUBCKT VNSE1 2 PARAMS: NLF = 10 FLW = 4NVR = 4.6
.PARAM GLF={PWR(FLW,0.25)*NLF/1164}
.PARAM RNV={1.184*PWR(NVR,2)}
.MODEL DVN D KF={PWR(FLW,0.5)/1E11} IS=1.0E-16
I1 0 7 10E-3
I2 0 8 10E-3
D1 7 0 DVN
D2 8 0 DVN
E1 3 6 7 8 {GLF}
R1 3 0 1E9
R2 3 0 1E9
R3 3 6 1E9
E2 6 4 5 0 10
R4 5 0 {RNV}
R5 5 0 {RNV}
R6 3 4 1E9
R7 4 0 1E9
E3 1 2 3 4 1
C1 1 0 1E-15
C2 2 0 1E-15
C3 1 2 1E-15
.ENDS
.SUBCKT FEMT1 2 PARAMS: NLFF = 0.1 FLWF = 0.001 NVRF = 0.1
.PARAM GLFF={PWR(FLWF,0.25)*NLFF/1164}
.PARAM RNVF={1.184*PWR(NVRF,2)}
.MODEL DVNF D KF={PWR(FLWF,0.5)/1E11} IS=1.0E-16
I1 0 7 10E-3
I2 0 8 10E-3
D1 7 0 DVNF
D2 8 0 DVNF
E1 3 6 7 8 {GLFF}
R1 3 0 1E9
R2 3 0 1E9
R3 3 6 1E9
E2 6 4 5 0 10
R4 5 0 {RNVF}
R5 5 0 {RNVF}
R6 3 4 1E9
R7 4 0 1E9
G1 1 2 3 4 1E-6
C1 1 0 1E-15
C2 2 0 1E-15
C3 1 2 1E-15
.ENDS
.SUBCKT PSRR_SINGLE VDDVSSVIVOGNDF PARAMS: PSRR = 130 FPSRR = 1.6
.PARAM PII = 3.141592
.PARAM RPSRR = 1
.PARAM GPSRR = {PWR(10,-PSRR/20)/RPSRR}
.PARAM LPSRR = {RPSRR/(2*PII*FPSRR)}
G1GNDF 1 VDD VSS {GPSRR}
R11 2 {RPSRR}
L12 GNDF {LPSRR}
E1VO VI 1 GNDF 1
C2VDD VSS 10P
.ENDS
.SUBCKT PSRR_SINGLE_NEW VDDVSSVIVOGNDF PARAMS: PSRR = 130 FPSRR = 1.6
.PARAM PII = 3.141592
.PARAM RPSRR = 1
.PARAM GPSRR = {PWR(10,-PSRR/20)/RPSRR}
.PARAM LPSRR = {RPSRR/(2*PII*FPSRR)}
G1GNDF 1 VDD VSS {GPSRR}
R11 2 {RPSRR}
L12 GNDF {LPSRR}
EA101 GNDF 1 GNDF 1
GRA101 102 VALUE = { V(101,102)/1e6 }
CA102 GNDF 1e3
EB1 1a VALUE = {V(102,GNDF)}
E1VO VI 1a GNDF 1
C2VDD VSS 10P
.ENDS
.SUBCKT PSRR_DUAL VDDVSSVIVOGNDF
+ PARAMS: PSRRP = 130 FPSRRP = 1.6
+ PSRRN = 130 FPSRRN = 1.6
.PARAM PII = 3.141592
.PARAM RPSRRP = 1
.PARAM GPSRRP = {PWR(10,-PSRRP/20)/RPSRRP}
.PARAM LPSRRP = {RPSRRP/(2*PII*FPSRRP)}
.PARAM RPSRRN = 1
.PARAM GPSRRN = {PWR(10,-PSRRN/20)/RPSRRN}
.PARAM LPSRRN = {RPSRRN/(2*PII*FPSRRN)}
G1GNDF 1 VDD GNDF {GPSRRP}
R11 2 {RPSRRP}
L12 GNDF {LPSRRP}
G2GNDF 3 VSS GNDF {GPSRRN}
R23 4 {RPSRRN}
L24 GNDF {LPSRRN}
E1VO VI VALUE = {V(1,GNDF) + V(3,GNDF)}
C3VDD VSS 10P
.ENDS
.SUBCKT PSRR_DUAL_NEW VDDVSSVIVOGNDF
+ PARAMS: PSRRP = 130 FPSRRP = 1.6
+ PSRRN = 130 FPSRRN = 1.6
.PARAM PII = 3.141592
.PARAM RPSRRP = 1
.PARAM GPSRRP = {PWR(10,-PSRRP/20)/RPSRRP}
.PARAM LPSRRP = {RPSRRP/(2*PII*FPSRRP)}
.PARAM RPSRRN = 1
.PARAM GPSRRN = {PWR(10,-PSRRN/20)/RPSRRN}
.PARAM LPSRRN = {RPSRRN/(2*PII*FPSRRN)}
G1GNDF 1 VDD GNDF {GPSRRP}
R11 2 {RPSRRP}
L12 GNDF {LPSRRP}
EA101 GNDF 1 GNDF 1
GRA101 102 VALUE = { V(101,102)/1e6 }
CA102 GNDF 1e3
EB1 1a VALUE = {V(102,GNDF)}
G2GNDF 3 VSS GNDF {GPSRRN}
R23 4 {RPSRRN}
L24 GNDF {LPSRRN}
EC301 GNDF 3 GNDF 1
GRC301 302 VALUE = { V(301,302)/1e6 }
CC302 GNDF 1e3
ED3 3a VALUE = {V(302,GNDF)}
E1VO VI VALUE = {V(1a,GNDF) + V(3a,GNDF)}
C3VDD VSS 10P
.ENDS
.SUBCKT CMRR VIVOGNDF PARAMS: CMRR = 130 FCMRR = 1.6K
.PARAM PII = 3.141592
.PARAM RCMRR = 1
.PARAM GCMRR = {PWR(10,-CMRR/20)/RCMRR}
.PARAM LCMRR = {RCMRR/(2*PII*FCMRR)}
G1GNDF 1 VI GNDF {GCMRR}
R11 2 {RCMRR}
L12 GNDF {LCMRR}
E1VI VO 1 GNDF 1
.ENDS
.SUBCKT CMRR_NEW VIVOGNDF PARAMS: CMRR = 130 FCMRR = 1.6K
.PARAM PII = 3.141592
.PARAM RCMRR = 1
.PARAM GCMRR = {PWR(10,-CMRR/20)/RCMRR}
.PARAM LCMRR = {RCMRR/(2*PII*FCMRR)}
G1GNDF 1 VI GNDF {GCMRR}
R11 2 {RCMRR}
L12 GNDF {LCMRR}
EA101 GNDF 1 GNDF 1
GRA101 102 VALUE = {V(101,102)/1e6}
CA102 GNDF 1e3
EB1 1a VALUE = {V(102,GNDF)}
E1VI VO 1a GNDF 1
.ENDS
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